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subroutine and pipelining capabilities (multi-cycle).

subroutine and pipelining capabilities (multi-cycle).

DO not bother looking at this question if you do not have a computer engineering background : The question is to implement a single cycle MIPS datapath and then extend it to include subroutine and pipelining capabilities (multi-cycle).

IF YOU DO NOT HAVE COMPUTER ENGINEERING BACKGROUND PLEASE STAY AWAY(i.e REFRAIN) FROM BIDDING FOR THIS QUESTION AS YOU WILL BE CONSIDERED A REAL NUISANCE AND A WASTE OF TIME.

This QUESTION includes anything from designing with basic blocks, to using VHDL/Verilog black boxes- must ensure that the model works with the Simulink environment provided in Matlab.

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